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4-BIT BIDIRECTIONAL COUNTERS (WITH 3-STATE OUTPUTS)
The MC54/ 74F568 and MC54/74F569 are fully synchronous, reversible counters with 3-state outputs. The F568 is a BCD decade counter; the F569 is a binary counter. They feature preset capability for programmable operation, carry lookahead for easy cascading, and a U/D input to control the direction of counting. For maximum flexibility there are both synchronous and master asynchronous reset inputs as well as both Clocked Carry (CC) and Terminal Count (TC) outputs. All state changes except Master Reset are initiated by the rising edge of the clock. A HIGH signal on the Output Enable (OE) input forces the output buffers into the high impedance state but does not prevent counting, resetting or parallel loading.
MC54/74F568 MC54/74F569
4-BIT BIDIRECTIONAL COUNTERS (WITH 3-STATE OUTPUTS)
FASTTM SCHOTTKY TTL
* 4-Bit Bidirectional Counting * * * * * *
F568 Decade Counter F569 Binary Counter Synchronous Counting and Loading Lookahead Carry Capability for Easy Cascading Preset Capability for Programmable Operation 3-State Outputs for Bus Organized Systems Master Reset (MR) Overrides All Other Inputs Synchronous Reset (SR) Overrides Counting and Parallel Loading
20 1
J SUFFIX CERAMIC CASE 732-03
20 1
N SUFFIX PLASTIC CASE 738-03
CONNECTION DIAGRAM
VCC TC 20 19 CC 18 OE 17 O0 16 O1 15 O2 14 O3 CET 13 12 PE 11
20 1
DW SUFFIX SOIC CASE 751D-03
ORDERING INFORMATION
MC54FXXXJ Ceramic MC74FXXXN Plastic MC74FXXXDW SOIC 1 U/D 2 CP 3 P0 4 P1 5 P2 6 P3 8 7 CEP MR 9 10 SR GND
LOGIC SYMBOL
11 3 4 5 6 P3
PE P0 P1 P2 1 7 12 2 17 U/D CEP
CC CET TC CP OE MR SR 8 9 O0 O1 O2 O3 16 15 14 13
18 19
FAST AND LS TTL DATA 4-220
MC54/74F568 * MC54/74F569
Symbol VCC TA IOH IOL Supply Voltage Operating Ambient Temperature Range Output Current -- High Output Current -- Low Parameter 54, 74 54 74 54, 74 54, 74 Min 4.5 - 55 0 Typ 5.0 25 25 Max 5.5 125 70 - 3.0 24 Unit V C mA mA
FUNCTIONAL DESCRIPTION The F568 counts modulo-10 in the BCD (8421) sequence. From state 9 (HLLH) it will increment to 0 (LLLL) in the Up mode; in Down mode it will decrement from 0 to 9.The F569 counts in the modulo-16 binary sequence. From state 15 it will increment to state 0 in the Up mode; in the Down mode it will decrement from 0 to 15. The clock inputs of all flip-flops are driven in parallel through a clock buffer. All state changes (except due to Master Reset) occur synchronously with the LOWto-HIGH transition of the Clock Pulse (CP) input signal. The circuits have five fundamental modes of operation, in order of precedence: asynchronous reset, synchronous reset, parallel load, count and hold. Five control inputs -- Master Reset (MR), Synchronous Reset (SR), Parallel Enable (PE), Count Enable Parallel (CEP) and Count Enable Trickle (CET) -- plus the Up/Down (U/D) input, determine the mode of operation, as shown in the Mode Select Table. A LOW signal on MR overrides all other inputs and asynchronously forces the flip-flop Q outputs LOW. A LOW signal on SR overrides counting and parallel loading and allows the Q outputs to go LOW on the next rising edge of CP. A LOW signal on PE overrides counting and allows information on the Parallel Data (Pn) inputs to be loaded into the flip-flops on the next rising edge of CP. With MR, SR and PE HIGH, CEP and CET permit counting when both are LOW. Conversely, a HIGH signal on either CEP or CET inhibits counting. The F568 and F569 use edge-triggered flip-flops and changing the SR, PE, CEP , CET or U/D inputs when the CP is in either state does not cause errors, provided that the recommended setup and hold times, with respect to the rising edge of CP, are observed. Two types of outputs are provided as overflow/underflow indicators. The Terminal Count (TC) output is normally HIGH and goes LOW providing CET is LOW, when the counter reaches zero in the Down mode, or reaches maximum (9 for the F568,15 for the F569) in the Up mode. TC will then remain LOW until a state change occurs, whether by counting or presetting, or until U/D or CET is changed. To implement synchronous multistage counters, the connections between the TC output and the CEP and CET inputs can provide either slow or fast carry propagation. Figure A shows the connections for simple ripple carry, in which the clock period must be longer than the CP to TC delay of the first stage, plus the cumulative CET to TC delays of the intermediate stages, plus the CET to CP setup time of the last stage. This total delay plus setup time sets the upper limit on clock frequency. For faster clock rates, the carry lookahead connections shown in Figure B are recommended. In this scheme the ripple delay through the intermediate stages commences with the same clock that causes the first stage to tick over from max to min in the Up mode, or min to max in the Down mode, to start its final cycle. Since this final cycle takes 10 (F568) or 16 (F569) clocks to complete, there is plenty of time for the ripple to progress through the intermediate stages. The critical timing that limits the clock period is the CP to TC delay of the first stage plus the CEP to CP setup time of the last stage. The TC output is subject to decoding spikes due to internal race conditions and is therefore not recommended for use as a clock or asynchronous reset for flip-flops, registers or counters. For such applications, the Clocked Carry (CC) output is provided. The CC output is normally HIGH. When CEP, CET, and TC are LOW, the CC output will go LOW when the clock next goes LOW and will stay LOW until the clock goes HIGH again, as shown in the CC Truth Table. When the Output Enable (OE) is LOW, the parallel data outputs O0-O3 are active and follow the flip-flop Q outputs. A HIGH signal on OE forces O0-O3 to the High Z state but does not prevent counting, loading or resetting. LOGIC EQUATIONS: Count Enable = CEPCETPE Up ('F568): TC = Q0Q1Q2Q3(Up)CET ('F569): TC = Q0Q1Q2Q3(Up)CET Down (Both): TC = Q0Q1Q2Q3(Down)CET CC TRUTH TABLE
Inputs SR L X X X X H PE X L X X X H CEP X X H X X L CET X X X H X L TC* X X X X H L CP X X X X X Output CC H H H H H
* = TC is generated internally L = LOW Voltage Level H = HIGH Voltage Level
X = Don't Care = Low Pulse
FUNCTION TABLE
Inputs MR L h h h h h h SR X l h h h H H PE X X l h h H H CEP X X X l l H X CET X X X l l X H U/D X X X h l X X CP X X X Operating Mode Asynchronous reset Synchronous reset Parallel load Count up (increment) Count down (decrement) Hold (do nothing)
H = HIGH voltage level h = HIGH voltage level one setup prior to the Low-to-High Clock transition L = LOW voltage level l = LOW voltage level one setup prior to the Low-to-High clock transition X = Don't care = Low-to-High clock transition
FAST AND LS TTL DATA 4-221
LOGIC DIAGRAMS MC54/74F568 MC54/74F569
P0
P1
P2
P3
P0
P1
P2
P3
PE
PE
CEP
CEP
CET
CET
T
LD
T
LD
AT AF TC
AT AF
TC
MC54/74F568 * MC54/74F569
FAST AND LS TTL DATA
CC LD T BT BF U/D DETAIL A DETAIL A CP UP DN SR UP DN CP ENF CD Q SR ENF LD T BT BF UP DETAIL A DETAIL A DN CP ENF CD Q SR CP CP J Q CP K CD Q SR DETAIL A MR OE O1 O2 O3 O0 O1 Q CD
4-222
Please note that these diagrams are provided only for the understanding of logic operations and should not be used to estimate propagation delays.
ENF
CC
U/D
UP
DN
DETAIL A
DETAIL A CP
SR
CP
CP
J
CP
Q
K CD Q
SR
DETAIL A
Q CD
MR
OE
O0
O2
O3
MC54/74F568 * MC54/74F569
Figure A. Multistage Counter with Ripple Carry
COUNT CET TC CP CET TC CET TC CET TC CET
CP
TO ALL STAGES
Figure B. Multistage Counter with Lookahead Carry
COUNT
CET TC L CP TO ALL STAGES
CEP CET TC
CEP CET TC
CEP CET TC
CEP CET
CP
DC CHARACTERISTICS OVER OPERATING TEMPERATURE RANGE (unless otherwise specified)
Limits Symbol Parameter Min VIH VIL VIK VOH VOL IOZH IOZL IIH Input HIGH Voltage Input LOW Voltage Input Clamp Diode Voltage 54, 74 Output HIGH Voltage 74 Output LOW Voltage Output OFF Current -- HIGH Output OFF Current -- LOW Input HIGH Current 100 Input LOW Current PE, CET Others Output Short Circuit Current (Note 2) Power Supply Current (ALL Outputs OFF) - 60 -1.2 -0.6 -150 67 2.7 3.3 0.3 0.5 50 - 50 20 V V A A A 2.4 3.3 2.0 0.8 - 1.2 Typ Max V V V V Guaranteed Input HIGH Voltage for All Inputs Guaranteed Input LOW Voltage for All Inputs VCC = MIN, IIN = - 18 mA IOH = - 3.0 mA IOH = - 3.0 mA IOL = 24 mA VOUT = 2.7 V VOUT = 0.5 V VIN = 2.7 V VIN = 7.0 V VCC = 4.5 V VCC = 4.75 V VCC = MIN VCC = MAX VCC = MAX VCC = MAX Unit Test Conditions
IIL IOS ICC
mA mA mA
VCC = MAX, VIN = 0.5 V VOUT = 0 V VCC = MAX VCC = MAX
NOTES: 1. For conditions such as MIN or MAX, use the appropriate value specified under recommended operating conditions for the applicable device type. 2. Not more than one output should be shorted at a time, nor for more than 1 second.
FAST AND LS TTL DATA 4-223
MC54/74F568 * MC54/74F569
STATE DIAGRAMS MC54/74F568
0 1 2 3 0 1
MC54/74F569
2
3
4
15 10 9 11 14 13 15 4 13 14
5
6
7
8
7
6
5
12
12
11
10
9
8
COUNT DOWN COUNT UP
COUNT DOWN COUNT UP
AC CHARACTERISTICS
54 / 74F TA = + 25C VCC = + 5.0 V CL = 50 pF Symbol fmax tPLH tPHL tPLH tPHL tPLH tPHL tPLH tPHL tPLH tPHL tPLH tPHL tPLH tPHL tPHL tPZH tPZL tPHZ tPLZ Parameter Maximum Clock Frequency Propagation Delay CP to On (PE HIGH or LOW) Propagation Delay CP to TC Propagation Delay CET to TC Propagation Delay U/D to TC (F568) Propagation Delay U/D to TC (F569) Propagation Delay CP to CC Propagation Delay CEP, CET to CC Propagation Delay MR to On Output Enable Time OE to On Output Disable Time OE to On Min 100 3.0 4.0 5.5 4.0 2.5 2.5 3.5 4.0 3.5 4.0 2.5 2.0 2.5 4.0 5.0 2.5 3.0 1.5 2.0 8.5 11.5 15.5 11 6.0 8.0 11 16 11 10.5 7.0 6.0 6.5 11 13 7.0 8.0 6.5 6.0 Max 54F TA = - 55 to + 125C VCC = 5.0 V 10% CL = 50 pF Min 60 3.0 4.0 5.5 4.0 2.5 2.5 3.5 4.0 3.5 4.0 2.5 2.0 2.5 4.0 5.0 2.5 3.0 1.5 2.0 10.5 14 18.5 13.5 8.0 10 13.5 19 13.5 13 9.0 8.0 8.5 13.5 15.5 9.0 10 8.5 8.0 Max 74F TA = 0 to + 70C VCC = 5.0 V 10% CL = 50 pF Min 85 3.0 4.0 5.5 4.0 2.5 2.5 3.5 4.0 3.5 4.0 2.5 2.0 2.5 4.0 5.0 2.5 3.0 1.5 2.0 9.5 13 17.5 12.5 7.0 9.0 12.5 18 12.5 12 8.0 7.0 7.5 12.5 14.5 8.0 9.0 7.5 7.0 Max Unit MHz ns ns ns ns ns ns ns ns ns ns
FAST AND LS TTL DATA 4-224
MC54/74F568 * MC54/74F569
AC OPERATING REQUIREMENTS
54 / 74F TA = + 25C VCC = + 5.0 V Symbol ts(H) ts(L) th(H) th(L) ts(H) ts(L) th(H) th(L) ts(H) ts(L) th(H) th(L) ts(H) ts(L) ts(H) ts(L) th(H) th(L) ts(H) ts(L) th(H) th(L) tw(H) tw(L) tw(L) trec Parameter Setup Time, HIGH or LOW Pn to CP Hold Time, HIGH or LOW Pn to CP Setup Time, HIGH or LOW CEP or CET to CP Hold Time, HIGH or LOW CEP or CET to CP Setup Time, HIGH or LOW PE to CP Hold Time, HIGH or LOW PE to CP Setup Time, HIGH or LOW U/D to CP (F568) Setup Time, HIGH or LOW U/D to CP (F569) Hold Time, HIGH or LOW U/D to CP Setup Time, HIGH or LOW SR to CP Hold Time, HIGH or LOW SR to CP CP Pulse Width HIGH or LOW MR Pulse Width, LOW MR Recovery Time Min 4.0 4.0 3.0 3.0 5.0 5.0 0 0 8.0 8.0 0 0 11 16.5 11 7.0 0 0 10 8.0 0 0 4.0 6.0 4.5 6.0 Max 54F TA = - 55C to + 125C VCC = 5.0 V 10% Min 5.5 5.5 3.5 3.5 7.0 7.0 0 0 10 10 0 0 13.5 18.5 13.5 10 0 0 12 10.5 0 0 6.0 8.0 6.0 8.0 Max 74F TA = 0C to + 70C VCC = 5.0 V 10% Min 4.5 4.5 ns 3.5 3.5 6.0 6.0 ns 0 0 9.0 9.0 ns 0 0 12.5 17.5 12.5 8.0 0 0 11 9.5 ns 0 0 4.5 6.5 5.0 7.0 ns ns ns ns ns ns Max Unit
FAST AND LS TTL DATA 4-225

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